maxim integrated products 1 some revision s of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim - ic.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1 - 888- 629- 4642, or visit maxim?s website at www.maxim - ic.com. ds31408 8- input, 14- output, dual dpll timing ic with sub - ps output jitter and 1588 clock general description the ds31408 is a flexible, high - performance timing ic for diverse frequency conversion and frequency synthesis appl ications. on each of its eight input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2khz and 750 mhz. the device offers two independent dplls to serve two independent clock - generation paths. the input clock s are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. the best input clock is selected, manually or automatically, as the reference clock for each of the two flexible, high - performance digital pl ls. each dpll lock to the selected reference and provides programmable bandwidth, very high resolution holdover capability , and truly hitless switching between input clocks. the digital plls are followed by a clock synthesis subsystem that has seven fully programmable digital frequency synthesis block s, three high - speed low - jitter aplls, and 14 output clocks, each with its own 32- bit divider and phase adjustment. the aplls provide fractional scaling and output jitter less than 1ps rms . for telecom systems, the ds31408 has all required features and functions to serve as a central timing function or as a line card timing ic. in addition the ds31408 has an embedded ieee 1588 clock that can be steered by system software to follow a time master elsewhere in the system or elsewhere in the network. this clock has all necessary features to be the central time clock in a 1588 ordinary clock, boundary clock or transparent clock. applications frequency conversion and ieee1588 time/frequency applications in a wide varie ty of equipment types telecom line cards or timing cards with any mix of sonet/sdh, synchronous ethernet and/or otn ports in wan equipment including mspps, ethernet switches, routers, dslams, and base stations ordering information part temp range pin - pack age ds31408gn - 40 c to +85 c 256 csbga ds31408 gn+ - 40 c to +85 c 256 csbga + denotes a lead (pb) - free/rohs - compliant package. spi is a trademark of motorola, inc. features ? eight input clocks ? differential or cmos/ttl format ? any frequency from 2khz to 750m hz ? fractional scaling for 64b/66b and fec scaling (e.g. , 64/66, 237/255, 238/255) or any other downscaling requirement ? continuous input clock quality monitoring ? two high - performance dplls ? hitless ref er ence switching on loss of input ? automatic or manual pha se build - out ? holdover on loss of all inputs ? programmable bandwidth, 0.5m hz to 400hz ? seven digital frequency synthesizers ? each can slave to either dpll ? pro duce any 2 khz multiple u p to 77.76 mhz ? three output aplls ? output frequencies to 750 mhz ? high resolution fractional scaling for fec and 64b/66b (e.g. , 255/237, 255/238, 66/64 ) or any other scaling requirement ? less than 1ps rms output jitter ? simultaneously produce three low - jitter rates from the same ref erence ( e.g. , 622.08mhz for sonet, 255/237*622.08mhz for otu2, and 156.25mhz for 10ge ) ? 14 output clocks in seven groups ? nearly any frequency from < 1hz to 750 mhz ? each group slave s to a dfs clock, any apll clock, or an y input clock (divided and scaled) ? each has a differential output ( 3 cml, 4 lvds/ lvpecl ) and separate cm os/ttl output ? 32- bit frequency divider per output ? ieee 1588 clock features ? steerable by software with 2 - 8 ns time resolution and 2 - 32 ns frequency resolution ? 4ns input timestamp accuracy and output edge placement accuracy ? programmable clock and time - alignment i/o to synchronize all 1588 devices in large s ystems ? supports 1588 oc, bc , and tc a rchitectures ? genera l features ? suitable line card ic or timing card ic for stratum 2/ 3 e/3/ 4 e/4, smc, sec/eec , or ssu ? accepts and produces nearly any frequenc y from 1hz u p to 750 mhz ? internal compensation for local oscillator frequency error ? s pi? processor interface ? 1.8v operation with 3.3v i/o (5v tolerant) 19 - 5659; rev 4 ; 7 /11 abridged data sheet
ds31408 2 a pplication example s typical timing card application example ds31408 to bits/ssu tcxo or ocxo monitor, divider, selector dpll1 apll and divider bits tx dpll2 bits rx processor timing card (1 of 2) backplane ds1, e1 or 2048 khz from bits/ssu timing card (2 of 2) identical to timing card 1 line card (1 of n) line card (n of n) <1> <1> <1> <1> n n n n typically 19.44mhz, 25mhz or 8khz, point-to-point or multidrop buses create derived ds1 or e1/2048khz clock locked to selected clock activity and frequency monitoring, select highest priority valid input for each dpll clock/data recovery, equalizer, framer, extract ssms stratum 2, 3e or 3: jitter/wander filtering, hitless switching, phase adjust, holdover selects best system clock, best recovered line clock. hitless switching, frequency conversion, jitter cleanup <0> <0> apll, divider and fanout line card timing ic (see fig 2-2) to port serdes from port serdes abr idged data sheet
ds31408 3 typical line card application example , traditional frequency synchronization dpll1 path system timing from master and slave timing cards ic1 ds31408 dpll2 path ic2 19.44mhz, 38.88mhz, 25mhz, etc. line timing to master and slave timing cards 8khz, 19.44mhz, 38.88mhz, 25mhz, etc. oc6 oc7 n recovered line clocks from serdes sonet/sdh, 1ge, 10ge, otn, fc etc. frequencies can be unrelated to one another 155.52m, 622.08m , 25m, 125m, 156.25m, etc. with or without fractional scaling for fec, 64b/66b, etc. many other rates possible, including ds1, e1, ds3, e3, 10m and nx19.44m. ic3 to ic8 n 3 unrelated frequencies simultaneously with <1ps rms jitter plus other frequencies with somewhat higher jitter clock monitoring and selection, undo fractional scaling, frequency conversion clock monitoring and selection, hitless switching, holdover, frequency conversion, fractional scaling, jitter attenuation oc1 to oc5 clocks to line card serdes sonet/sdh, 1ge, 10ge, otn, fc, etc. typical application example , frequency and time synchronization system time, e.g. 1 pps to all port cards line clocks, e.g. 25mhz from port cards, for synce or 1588+synce operation ds31408 spi local osc tcxo or ocxo system clock, e.g. 25mhz other clocks processor 1588 software packet data to/from central switch function dpll 1588 clock abridged data sheet
ds31408 4 block diagram dpll1 filtering, holdover, hitless switching, pbo, frequency conversion, manual phase adjust master clock apll fsync mfsync ic5 pos/neg ic6 pos/neg microprocessor port (spi serial) and hw control and status pins local oscillator tcxo or ocxo rst cs cpha sclk sdi sdo intreq dpll2 identical to dpll1 srcsw mclkosc jtag sync1 test gpio[4:1] srfail lock sync3 ic1 pos/neg ic2 pos/neg sync2 oc1pos/neg oc7pos/neg oc4 cpol jtrst jtms jtclk jtdi jtdo dfs 4 dfs 5 dfs 6 dfs 7 dfs 1 oc5 oc6 oc7 oc1 mfsync ds31408 apll1 lowest jitter path pll bypass oc4pos/neg oc5pos/neg oc6pos/neg ic3 pos/neg ic4 pos/neg ic7 pos/neg ic8 pos/neg oscfreq[2:0] divider 1 dfs muxes divider muxes dif muxes input clock block frequency scaler, activity monitor, freq. monitor, optional inversion (per input clock) clock selector 8 status oc2pos/neg dfs 2 oc2 apll2 lowest jitter path divider 2 oc3pos/neg dfs 3 oc3 apll3 lowest jitter path divider 3 divider 5 divider 6 divider 7 divider 4 1588 time engine clkin tain mclk icx icx ocx ocx syncx out1 out2 to divider muxes 1588 out1 1588 out2 abridged data sheet
ds31408 5 detailed features input clock features ? eight input clocks, differential or cmos/ttl signal format ? input clocks can be any frequency from 2khz up to 750 mhz ? supported telecom frequencies include pdh, sdh, synchronou s ethernet, otu - 1, otu - 2, otu -3 ? per - input fractional scaling (i.e. , multiplying by n d where n is a 16 - bit integer and d is a 32- bit integer and n < d ) to undo 64b/66b and fec scaling (e.g. , 64/66, 238/255, 237/255, 236/255) ? special mode allows locking to 1hz input clocks ? all inputs constantly monitored by programmable activity monitors and frequency monitors ? fast activity monitor can disqualify the selected reference after a few missing clock cycles ? frequency measurement and frequency monitor thresholds wi th 0. 2 ppm resolution ? three optional 2/4/8khz frame - sync inputs dpll features ? very high - resolution dpll architecture ? sophisticated state machine automatically transitions between free - run, locked, and holdover states ? revertive or nonrevertive reference sele ction algorithm ? programmable bandwidth from 0.5m hz to 400hz ? separately configurable acquisition bandwidth and locked bandwidth ? programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 , or 20 ? multiple phase detectors: phase/frequency and multicycle ? phase/frequency locking ( 360 capture) or nearest edge phase locking ( 180 capture) ? multicycle phase detection and locking (up to 8191ui) improves jitter tolerance and lock time ? phase build - out in response to reference switching for true hitless switching ? less than 1 ns output clock phase transient during phase build -out ? output phase adjustment up to 200ns in 6ps steps with respect to selected input reference ? high - resolution frequency and phase measurement ? holdover frequency averaging ove r 1 - second, 5.8- minute , and 93.2 - minute intervals ? fast detection of input clock failure and transition to holdover mode ? low - jitter frame sync (8khz) and multiframe sync (2khz) aligned with output clocks digital frequency synthesizer features ? seven indepen dently programmable dfs block s ? each dfs can slave to either of the dplls ? each dfs can synthesize any 2 kh z multiple up to 77.76 mhz ? per - dfs phase adjust (1/256ui steps) ? approximately 4 0ps rms output jitter output apll features ? simultaneously produce three hi gh- frequency, low - jitter, rates from the same reference clock, e.g. , 622.08mhz for sonet, 255/237*622.08mhz for otu2, and 156.25mhz for 10ge ? standard telecom output frequencies include 622.08mhz , 155.52mhz , and 19.44mhz for sonet/sdh and 15 6.25mhz, 125mhz , and 25mhz for synchronous ethernet ? very high - resolution fractional scaling (i.e. , noninteger multiplication ) ? less than 1 ps rms output jitter abridged data sheet
ds31408 6 output clock features ? 14 output clock signals in seven groups ? o utput clock groups oc1 , oc2, oc3 have a very high -s peed differential output (current - mode logic, 750mh z) and a separate cmos/ttl output ( 125mh z) ? output clock groups oc4 ? oc7 have a high - speed differential output (lvds/lvpecl, 312.5 mhz) and a separate cmos/ttl output ( 125mhz ) ? supported telecom frequencies include pdh, sdh, synchronous ethernet, otu - 1, otu - 2, otu -3 ? internal clock muxing allows each output group to slave to its assoc iated dfs block, any of the aplls, or any input clock (after being divided and scaled) ? outputs sourced direct ly from aplls have less than 1 ps rms output jitter ? outputs sourced directly from dfs block s have approximately 4 0ps rms output jitter ? optional 32 - bit frequency divider per output ? 8khz frame sync and 2khz multiframe sync outputs have programmable polarity and pulse width and can be disciplined by a 2khz or 8khz f rame sync input ? per - output delay adjust ment ? per - output enable/ disable ? all outputs disabled during reset 1588 clock features ? initialized and steered by software on an external processor to follow a n external 1588 master ? 2 - 8 ns time r esolution and 2 - 32 ns fr equency resolution ? 4ns accuracy for input signal timestamping and output signal edge placement ? three time/frequency controls: direct time write, high - resolution frequency adjustment, and time adjustment (i.e. , frequency adjustment for an exact duration to achieve gradual, precise time change) ? programmable clock and time - alignment i/o to synchronize all 1588 elements in large systems o can frequency - lock to an input clock signal from a master elsewhere in the system o can timestamp (ts) an input alignment signal to time - lock to a master elsewhere in the system (e.g. , 1pps) o can provide an output clock signal to slave components elsewhere in the system (e.g. , 25mhz) o can provide an output time alignment signal to slaves elsewhere in the system (e.g. , 1 pps) ? two f lexi ble programmable event generator s (peg) can output one pulse per second (1 pps) , one pulse per period, and a wide variety of clock signals ? full support for dual redundant timing cards for high - reliability, fault - tolerant systems ? compatible with a wide vari e ty of 1588 system architectures for 1588 ordinary clocks, boundary clocks , and transparent clocks general features ? spi serial microprocessor interface ? four general - purpose i/o pins ? register set can be write - protected ? operates from a 12.8mhz, 25.6mhz, 10.24 mhz, 20.48mhz, 10mhz, 20mhz, 19.44mhz , or 38.88mhz local oscillator ? on - chip watchdog circuit for the local oscillator ? internal compensation for local oscillator frequency error note to readers: this document is an abridged version of the full data sheet. to request the full data sheet, go to www.maxim - ic.com/ds31408 and click on request full data sheet . abridged data sheet
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